|GNU Make Manual||www.imodulo.com · 2003-04-05|
|[ Software | Documentation | Contact ]|
makeDeduce the Commands
It is not necessary to spell out the commands for compiling the individual C source files, because
make can figure them out: it has an implicit rule for updating a
.o file from a correspondingly named
.c file using a
cc -c command. For example, it will use the command
cc -c main.c -o main.o to compile
main.o. We can therefore omit the commands from the rules for the object files. Using Implicit Rules.
.c file is used automatically in this way, it is also automatically added to the list of prerequisites. We can therefore omit the
.c files from the prerequisites, provided we omit the commands.
Here is the entire example, with both of these changes, and a variable
objects as suggested above:
objects = main.o kbd.o command.o display.o \ insert.o search.o files.o utils.o edit : $(objects) cc -o edit $(objects) main.o : defs.h kbd.o : defs.h command.h command.o : defs.h command.h display.o : defs.h buffer.h insert.o : defs.h buffer.h search.o : defs.h buffer.h files.o : defs.h buffer.h command.h utils.o : defs.h .PHONY : clean clean : rm edit $(objects)
Because implicit rules are so convenient, they are important. You will see them used frequently.
|© Free Software Foundation, Inc.|